A page fault occurs (1) when a page is referenced which is part of the process's code or data regions, but is not currently loaded in memory or (2) when a page is referenced which is not in the process's code or data regions.

If VPN had been 07 and set 3, we would have had a TLB miss.

The page table entry for VPN 07 would have to be fetched from memory.

But that page table entry is

      VPN  PPN  Valid
      07    -     0
   

The page is NOT in memory. So the MMU hardware generates a page fault.

The operating system page fault handler then must determine if the page belongs to any of the process's code or data regions. For now assume it does.

The page fault handler then must fetch the page from disk! (~100,000 times slower)

Then the Page Table must be updated and the entry changed to valid.

The TLB cache is also updated.

Then what?