     _______ _______         
     |Dev 1| |Dev 2|  ...
     |_____| |_____|
       |      |
       |s1    |          CONTROL
     __|______|__   s2->   BUS
     |Interrupt |---------+   |
     |Controller|   <-s4  |   |
     |   Chip   |-------------+
     |__________|   s5->  |   |      |
                 --------------------+
                          |   |      |
                      INTR|   |INTA  |
      CPU                 |   |      |
________________   <-s2   |   |      |DATA
| ALU  | CU    |----------+   |      |BUS
|      |       |   s4->       |      |
|      |       |--------------+      |
|--------------|    <-s7    <-s5     |
|PC<--s7--<-MDR|---------------------+
|PS      |     |    s3->             |
|     s5 |     |             s6->    |    |
|        +->MAR|--------------------------+
|______________|                     |    |
                                     |    |s6
    Memory                      DATA |    |
 _____________                     s3|    |
 |        |  |                     s7|    |ADDR
 |        |__|                       |    |BUS
 |Int Vec.|  |                       |    | 
 |        |__|     <-s6   s7->       |    |
 |        |__|-----------------------+----+
 |           |                       |    |
 |Proc.Tbl.  |______<-s3_____________|
 |-----------|                       |
 |savPS|savPC|                       |
 |___________|                       |

CPU Hardware Actions when Accepting a Device Interrupt
s1. Device 1 signals an interrupt to interrupt controller chip.
s2. Interrupt controller chip signals interrupt to CPU.
s3. CPU saves PC and PS registers in the entry in the Process Table (in Memory) for the interrupted process.
s4. CPU acknowledges the interrupt.
s5. Interrupt Controller chip sends number identifying the device.
s6. CPU uses the value from s5 to get entry address in the interrupt vector and reads this entry.
s7. Entry is returned along the data bus and CPU loads the entry into the PC and PS registers.

Hardware Interrupts