Processors can be set to ignore or to respond to interrupts.

If an interrupt is currently masked (ignored), it remains pending. When interrupt is enabled again on the processor, the interrupt action occurs.

Hardware architecture possibilities:

• Interrupt class corresponds to a bit in a register; os masks/unmasks an interrupt class by setting/clearing the bit for that class.

  When an interrupt occurs and is not previously masked, the bit is set (masked) while the handler executes and cleared when the handler returns.

• Interrupt Priority Level - integer in a register. Interrupt class integer smaller than the current IPL register are masked.

  When an interrupt does occur and the handler is invoked, the IPL register is set to the interrupt priority level of the handler. When the handler returns the IPL register is restored to its previous value.