The physical address 0x357 was determined by the MMU hardware in the cpu from the virtual address since there was a hit in the TLB for the page table entry.

Now a lookup in the L1 cache would check to see if the contents of the physical address are available (a hit in the L1 cache).

Summary:

• The TLB cache in the CPU is used to try to translate the virtual address without having to access the page table in memory.

• After the virtual address has been translated, the L1 cache is used to try to access the data at the physical address without having to access the actual physical location in main memory.

If a cache miss occurs in either case, memory must be accessed. (In this case the corresponding cache is updated.)