CSC343 HW1

  1. Many machine instructions are "privileged". For example, instruction to halt the machine. Suppose a user program is written in assembly language using some of these privileged instructions. What prevents the privileged instructions in this user program from executing? 
    

    When a privileged instruction is about to be executed, the processor
hardware checks the mode bit in the PS register to ensure that the
processor is in "kernel" mode. If the processor is only in "user"
mode, the processor hardware does not execute the instruction.
  2. Suppose a cpu has an instruction to load the processor status register. Should this instruction be privileged or not? Explain briefly. 
    

Yes. This instruction should be privileged. A primary protection need
is to prevent user code from being executed in kernel mode in order to
prevent user code from corrupting kernel data structures and/or
interferring with other user programs. 

However if the load PS instruction were not privileged, a user
mode program could execute this instruction and replace the processor
status register with an arbitrary value. A value could easily be
determined that would have the mode bit set to kernel. This would
allow the user mode program to change to kernel mode and continue
executing the user code.
  3. How and when does the processor (cpu) notice that a device has generated an interrupt? 
    

In "step 4" of the cpu cycle, the cpu checks the interrupt line in the
control bus to see if any device has asserted this line, thereby
signaling an interrupt request from the device.
  4. If a hardware interrupt occurs, the cpu hardware causes the beginning address of an operating system Interrupt Service Routine to be loaded into the PC register and an appropriate PS value (with the kernel mode bit set) into the PS register. How does the cpu determine which PC/PS values to load and where are these PC/PS values located? 
    

First the cpu asserts a signal in the control bus acknowledging the
interrupt signal.

The interrupt controller chip responds to the cpu by placing an integer
value on the data bus identifying the (highest priority) interrupting
device. 

The cpu uses this value as the index (possibly multiplied by a scale
factor) into an array of PC/PS pairs. These pairs are located in
consecutive memory locations as an array known as the "interrupt
vector".
  5. Describe two ways in which a hardware interrupt is different from a software interrupt? 
    


    
1. A hardware interrupt is initiated by a hardware device; a software
interrupt is initiated by executing a special instruction.

    


    
2. A hardware interrupt is noticed and handled by the processor in
step 4 of the processor cycle; a software interrupt is handled when
the special instruction is executed - step 3 of the processor cycle.
  6. Why is a software interrupt useful as a mechanism for making system calls? 
    

Calling a routine involves changing the program counter, PC.

However, a system call in addition to changing the PC to address
kernel routine code must change the PS register as well. The PS
register must be set to indicate kernel mode.

Furthermore, it should not be possible to change only the PS register
without changing the PC register since this would allow the PC to
continue to be set to user code, but with the PS register set so the
cpu is in kernel mode.

This is precisely what a software interrupt does. It is an instruction
that simultaneously changes both the PC and the PS
registers. Furthermore the instruction doesn't allow the user to
directly specify the new PC and PS values. The new values are
determined only indirectly by specifying a number that corresponds to
a system routine. This means the software interrupt cannot be used
either inadvertently or maliciously to set the PS register to kernel
mode while keeping the PC pointing to user code.